1. Technical Field
The present invention relates to a method of manufacturing a semiconductor capable of preventing loss of a semiconductor substrate and a bit line.
2. Related Art
With the high integration degree of semiconductor devices, demand for dynamic random access memories (DRAMs) of below 40 nm grade has increased to further improve integration degree. However, it is very difficult to scale down below 40 nm in a planar or recess gate transistor used in 8 F2 (F: minimum feature size) or 6 F2 cell architecture. Accordingly, DRAMs having 4 F2 cell architecture have been demanded to improve the integration degree 1.5 to 2 times at the same scaling. Thus a vertical channel transistor has been suggested.
A vertical channel transistor is a transistor in which a channel is vertically formed by forming a surround type gate electrode around a pillar so that it extends vertically on a semiconductor substrate and forming a source region and a drain region in upper and lower portions of the active pillar with the gate electrode as the center, respectively. Thus, a larger the channel region may be maintained as the size of the transistor is reduced.
A channel (or channel region) of a vertical channel MOS transistor is formed to be vertical with respect to the surface of a semiconductor substrate by forming a gate electrode around an active pillar, which also extends vertically with respect to the surface of the semiconductor substrate, and forming a source and a drain in upper and lower portions with the gate electrode as the center. Thus, the channel length or region of the MOS transistor may be kept relatively large as the size of the MOS transistor is reduced. In implementing such a vertical channel semiconductor device, a technology in which the bit line is buried within a device isolation layer of a cell has been suggested.
According to the related art, a buried bit line in a vertical channel semiconductor device is formed by etching a semiconductor substrate with an etching condition that the buried bit line is self-aligned with the vertical pillar and an insulating layer formed around the vertical pillar. The buried bit line formed by such a method is in contact with the bit line contact, which is diffused and formed at a sidewall of the vertical pillar.
In an embodiment, the bit line contact is diffused into the semiconductor substrate to form a junction. However, when a titanium nitride layer or a tungsten layer is used to form the junction, leakage current increases as TiSi2 is generated. When a polysilicon layer is used in order to prevent this problem, resistance increases. Thereby, a method of performing a diffusion process after a metal layer is formed at a lower portion and a polysilicon layer is formed on the metal, is introduced.
Since a contact is open when an etch back process for the bit line is performed after the contact is formed by diffusing a metal layer at the lower portion, a portion of the semiconductor substrate may be lost. In addition, when the contact is formed after the bit line is formed, the bit line is also removed when stripping a metal spacer to open an area where the contact is to be formed.